through optimal generation and verification
of timing constraints.
with automated timing constraint
generation and verification.
workflow through intelligent timing
constraint generation and verification.
ASICSERVE
AI driven timing constraints generation – Automatic clock groups generation.
The Clock Groups Challenge
- In ASIC timing analysis, defining clock groups (asynchronous, logically exclusive, or physically exclusive clocks) is critical for accurate static timing analysis. Manual clock group definition is:
- Error-prone and time-consuming
- Requires deep design knowledge across multiple hierarchy levels
- Difficult to maintain as designs evolve
- Subject to human oversight, leading to false paths or missed timing violations
- Efficiency of automatic clock groups generation:
- Dramatically reduces constraint development time
- Scales to large designs with hundreds of clocks
- Adapts quickly to design changes
- Hybrid Approach:
- Best results likely come from AI suggesting clock groups with confidence scores, allowing engineers to review and approve, especially for:
- Safety-critical designs
- Novel clock architectures
- Mode-dependent scenarios
CLI (Command Line Interface) to AI for SDC Automatic Generation
- Seamless Integration into ASIC Design Flow
- CLI access to AI-powered SDC generation integrates naturally into existing ASIC development workflows:
- Engineer-Friendly:
- Works in your familiar terminal environment
- No context switching to web interfaces or GUIs
- Combines with standard Unix tools (grep, sed, diff) for constraint management
- Reproducible & Traceable:
- Command history provides audit trail of constraint decisions
- Easy to version control: commands and generated SDC together
- Reproduce results reliably across team members
Constraint Definition Through Natural Language – HAAL
- HAAL (High-Level Abstraction Asking Language) enables engineers to define timing constraints using natural, free-form language. By communicating directly with AI, you describe your timing intent - the AI translates it into precise SDC commands.
Example 1: Clock Grouping
- ASIC Engineer says:
- "Keep all generated clocks in the same group as their masters"
- AI generates:
- Precise SDC commands with grouped clock families, documented with clear intent
- AI confirms:
- Should these clock families be asynchronous to each other?"
- ASIC Engineer:
- "Yes, but I need specific paths between the main and peripheral domains to be analysed"
- AI responds:
tcl
# Asynchronous clock groups with selective path exceptions
set_clock_groups -asynchronous \
-group [get_clocks {clk_main gen_clk_div2 gen_clk_div4}] \
-group [get_clocks {clk_peripheral gen_clk_peri_gated}] \
-allow_paths
- AI asks:
- "Which specific paths between these domains should be analysed? For example, control signals, handshake paths, or synchronized data paths?"
- ASIC Engineer:
- "Only the handshake signals from the control module"
- AI refines:
- Should these clock families be asynchronous to each other?"
- ASIC Engineer:
- "Yes, but I need specific paths between the main and peripheral domains to be analysed"
- AI responds:
tcl
set_clock_groups -asynchronous \
-group [get_clocks {clk_main gen_clk_div2 gen_clk_div4}] \
-group [get_clocks {clk_peripheral gen_clk_peri_gated}] \
-allow_paths -from [get_pins control_module/handshake_*/Q] \
-to [get_pins peripheral_if/handshake_*_sync/D]
Result
- Production-ready, formally verified constraints - without writing a single line of SDC
- Key Benefits:
- Intuitive: Express constraints as you think about them - no SDC syntax required
- Interactive: AI asks clarifying questions to capture exact intent
- Handles complexity: Manages exceptions and special cases naturally
- Explainable: Generated SDC includes comments explaining the intent
- Iterative: Quickly refine constraints through natural conversation
- Verified: Integrate with formal verification tool to ensure correctness