Verilog / SystemVerilog

RTL Hierarchy.
Cross probing with design hierarchy.
RTL level SDC debugging.

Human AI Associative Language
Mixture of HAAL and SDC

Master clocks
Generated clocks
Clock groups
False paths
Multicycle paths

Clocks analysis
Clocks propagation
Clocks relations
Case analysis conflicts verification
False paths analysis
Multicycle paths analysis
CDC analysis
Power analysis
Formal verification