GeSTAR®
Generative STA for RTL
Closing the gap between RTL intent and correct SDC
ASIC design engineers
can generate production-ready SDC
in days, not months
by ASICSERVE 2026
Synopsys Certified Service Provider
The GeSTAR★ Flow
📄
RTL
Source
Verilog / SystemVerilog
🌳
RTL
Browser
Interactive RTL hierarchy.
Visual cross-probe.
RTL-level SDC debug.
🧠
Core IP
HAAL®
Layer
Human AI Associative Language
Plain-language intent → production SDC
⚙️
SDC
Generator
Master clocks
Generated clocks
Clock groups
False paths
Multicycle paths
🔌
UPF
Power intent · IEEE 1801
🔀
CDC/RDC Verifier
Clock-domain crossings
Synchronizer detection
Quasi-static / monotonic sources
Metastability protection
Reset-domain crossings
Async reset assertion / removal
Reset synchronizer & ordering checks
✅
SDC Verifier
Clock relations & propagation
Case-analysis conflicts
False / multicycle paths — formally proven · z3
UPF Verifier
Power-domain crossings
Isolation / level-shifter checks
Retention consistency
Power-state table legality
DFT Preview
OCC / test-clock intent
Shift · capture · at-speed modes
Test-mode SDC scaffolding
Clock controllability check
Sign-off
Verified SDC + CDC / UPF reports
Ready for STA & PnR
GeSTAR★Generative STA for RTL
HAAL In · SDC Out
HAAL — Human AI Associative Language · describing SDC intent in plain words, get production-ready SDC
You describe · HAAL
GeSTAR generates · SDC
“ref_clk_100 is a 100 MHz primary input clock.”
→
create_clock -name ref_clk_100 -period 10.0 [get_ports ref_clk_100]
“clk_core comes off the core PLL, running at 1 GHz.”
→
create_clock -name clk_core -period 1.0 [get_pins u_clk_rst/u_core_pll/clk_out0]
“clk_ddr and clk_ddr_2x are asynchronous — group them.”
→
set_clock_groups -name CG_ASYNC_DDR -asynchronous -group {clk_ddr clk_ddr_2x}
No hand-written constraints. No drift between intent and SDC — every line is generated, audited, and re-verifiable from the same plain-language source.
GeSTAR★Generative STA for RTL
Timing Analysis
report_timing · full launch / capture clock + data path — cross-probed to schematic & RTL source
⌘ GeSTAR Console · report_timing -nworst 1  ·  GB + RTL Browser
gestar> report_timing -nworst 1 -path clock
1
GeSTAR report_timing -nworst 1 — worst path on clk_core from r_halted_reg/CK to pc_reg[0]/D, with the full launch/capture clock path and data path cross-probed into the Graph Browser and RTL Browser
SCHEMATIC WALK1 / 3
6 levelsworst-path data depth report_timing -nworst 1 · launch & capture on clk_core (period 1.00 ns / 1 GHz) · full clock + data path
startpoint r_halted_reg/CK endpoint pc_reg[0]/D clock clk_core · 1.00 ns cross-probed → GB + RTL source
report_timing renders the full path — launch clock path, the data path (with Dir / Depth at each point), and the capture clock path — and cross-probes every point into the RTL schematic and the RTL source.
NOTE: path topology and clocking are shown straight from RTL.
GeSTAR★Generative STA for RTL
CDC Analysis
analyze_cdc · clock-domain-crossing check — traced straight from RTL with set_clock_groups intent
⌘ GeSTAR Console · analyze_cdc -visual  ·  Path Schematic + GB
gestar> analyze_cdc -visual
1
GeSTAR analyze_cdc -visual — 6 clock-domain pairs, 158 crossings, with the clk_ddr to clk_core path rendered in the Path Schematic and cross-probed into the Graph Browser
SCHEMATIC WALK1 / 3
158 crossingsacross 6 clock-domain pairs All 6 pairs declared async (set_clock_groups) · structural metastability review at RTL
clk_ddr → clk_core 45 crossings declared async 6 / 6 pairs flagged 5 unsafe-sync via locked · cal_done · s0_awready
CDC pairs come from set_clock_groups intent; crossings are traced structurally across the RTL netlist, and "unsafe-sync" marks a crossing with no recognized synchronizer on the path.
NOTE: structural CDC detection only — it locates and lets you review clock crossings early at RTL.
GeSTAR★Generative STA for RTL
Power Analysis
analyze_pwr · vectorless dynamic power — estimated straight from RTL, before sign-off
⌘ GeSTAR Console · analyze_pwr -histogram  ·  GB — Graph Browser
gestar> analyze_pwr -histogram
GeSTAR analyze_pwr -histogram — switching power by clock domain, with the soc_top design open in the Graph Browser
1
2
2.202 mW(2,201.9 µW) Estimated total dynamic (switching) power · 1,727 flops · 17 clock domains
clock-tree 83% registers 17% combinational 0% hottest: clk_core 1,040 µW (47%) clk_ddr 788 µW (36%)
Assumptions (vectorless): Vdd = 0.9 V · activity α = 0.1 · caps net = 3 fF, flop_out = 4 fF, clk_pin = 2 fF.
NOTE: first-order switching power only.
GeSTAR★Generative STA for RTL
Production-ready SDC.
In days, not months.
GeSTAR puts complete, sign-off-quality SDC in your hands at RTL — generated from intent, cross-probed to source, and verified before a single gate exists.
By ASICSERVE 2026
Synopsys Certified Service Provider